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_gain register. in cases where there is more than one possible mapping, the 2x ga in stage is enabled to provide the mapping with the lowest noise. when the aptina imaging gain model is in use and values have been written to the gain_ registers, data read from the associated analog ue_gain_code_ register is undefined. the reason for this is that many of the gain codes available in the aptina imaging gain model have no corr esponding value in the smia gain model. the result is that the two gain models can be used interchangeably, but having written gains through one set of registers, those gains should be read back through the same set of registers.
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 45 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor sensor core digital data path preliminary sensor core digital data path test patterns the MT9D014 supports a number of test pa tterns to facilitate system debug. test patterns are enabled using test_pattern_mode (r0x0600?1). the test patterns are listed in table 11. test patterns 0?3 replace pixel data in the output image (the embedded data rows are still present). test pattern 4 replaces all data in the output image (the embedded data rows are omitted and test pattern data replaces the pixel data). for all of the test patterns, the MT9D014 registers must be set appropriately to control the frame rate and output timing. these include: ?all clock divisors ? x_addr_start ? x_addr_end ? y_addr_start ? y_addr_end ? frame_length_lines ?line_length_pck ?x_output_size ? y_output_size the MT9D014 will disable digital corrections automatically when test patterns are acti- vated. the test cursor is now added to the end of the data path. solid color test pattern in this mode, all pixel data is replaced by fixed bayer pattern test data. the intensity of each pixel is set by its associated test data register (test_data_red, test_data_greenr, test_data_blue, test_data_greenb). 100 percent color bars test pattern in this test pattern, shown in figure 20 on page 46, all pixel data is replaced by a bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, and black). each bar is 200 pixels wide and occupies the full height of the output image. each color component of each bar is set to either ?0? (fully off ) or 0x3ff (fully on for 10-bit data). the pattern repeats after 8 * 200 = 1600 pixels. the image size is set by x_addr_start, x_addr_end, y_ad dr_start, y_addr_end and may be affected by the setting of x_output_size, y_output_size. the color-bar pattern starts at the column identified by x_addr_start. the number of colors that ar e visible in the output is dependent upon x_addr_end ? x_addr_start and the setting of x_output_size. the width of each color-bar is fixed at 200 pixels. table 11: test patterns test_pattern_mode description 0 normal operation: no test pattern 1 solid color 2 100% color bars 3 fade-to-gray color bars 4 pn9 link integrity pattern
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 46 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor sensor core digital data path preliminary the effect of setting horizontal_mirror in conjunction with this test pattern is that the order in which the colors are generated is reve rsed. the black bar appears at the left side of the output image. any pattern repeat occu rs at the right side of the output image regardless of the setting of horizontal_mirror. the state of vertical_flip has no effect on this test pattern. the effect of subsampling and sc aling of this test pattern is undefined. figure 20: 100 percent color bars test pattern fade-to-gray color bars test pattern in this test pattern, shown in figure 21 on page 47, all pixel data is replaced by a bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, and black). each bar is 200 pixels wide and occu pies 1024 rows of th e output image. each color bar fades vertically from full intensit y at the top of the image to 50 percent inten- sity (mid-gray) on the 1024th row. each color ba r is divided into a left and a right half, in which the left half fades smoothly and the right half fades in quantized steps every 8 pixels for a given color. due to the bayer patte rn of the colors this means that the level changes every 16 rows. the pattern repeats horizontally after 8 * 200 = 1600 pixels and vertically after 1024 rows (usi ng 10-bit data, the fade-to-gray pattern goes from 100 to 50 percent or from 0 to 50 percent for each color component, so only half of the 2 10 states of the 10-bit data are used. however, to get all of the gray levels, each state must be held for two rows, hence the vertical size of 2 10 / 2 * 2 = 1024). the image size is set by x_addr_start, x_addr_end, y_addr_start, and y_addr_end and may be affected by the setting of x_output_size and y_output_size. the color-bar pattern starts at the column identified by x_addr_start. the number of colo rs that are visible in the output is depen- dent upon x_addr_end ? x_ad dr_start and the setting of x_output_size. the width of each color-bar is fixed at 200 pixels. the effect of setting horizontal_mirror or vertical_flip in conjunction with this test pattern is that the order in which the colors are generated is reversed. the black bar appears at the left side of the output image. any pattern repeat occurs at the right side of the output image regardless of the setting of horizontal_mirror. the effect of subsampling and sc aling of this test pattern is undefined. horizontal mirror = 0 horizontal mirror = 1
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 47 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor sensor core digital data path preliminary figure 21: fade-to-gray color bars test pattern pn9 link integrity pattern this test pattern provides a 512-bit pseudo-ran dom test sequence to test the integrity of the serial pixel data output stream. the polynomial x 9 + x 5 + 1 is used. the polynomial is initialized to 0x1ff at the start of each frame. when this test pattern is enabled: ? the embedded data rows are disabled, an d the value of frame_ format_decriptor_1 changes from 0x1002 to 0x1000 to indicate that no rows of embedded data are present. ? the whole output frame, bounded by th e limits programmed in x_output_size and y_output_size, is fill ed with data from the pn9 sequence. ? the output data format is (effectively) fo rced into raw10 mode regardless of the state of the data_format register. this polynomial generates the following sequ ence of 10-bit values : 0x1ff, 0x378, 0x1a1, 0x336, 0x385, and so on. on the serial pixel data output, these values are streamed out sequentially without performing the raw10 packing to bytes that normally occurs on this interface. horizontal mirror = 0, vertical flip = 0 horizontal mirror = 0, vertical flip = 1 horizontal mirror = 1, vertical flip = 0 horizontal mirror = 1, vertical flip = 1
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 48 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor sensor core digital data path preliminary test cursors the MT9D014 supports one horizontal and one ve rtical cursor, allowing a ?cross hair? to be superimposed on the image or on test patterns 1?3. the position and width of each cursor ar e programmable in r0x31e8?0x31ee. each cursor can be inhibited by setting its width to ?0.? the programmed cursor position corresponds to an absolute row or column in the pixel array. for example, setting horizontal_cursor_ position to the same value as y_addr_start would result in a horizontal cursor being dr awn starting on the first row of the image. the cursors are opaque (they replace data fr om the imaged scene or test pattern). the color of each cursor is set by the values of the bayer components in the test_data_red, test_data_greenr, test_data_bl ue, and test_data_greenb registers. as a consequence, the cursors are the same color as test pattern 1 and are therefore invisible when test pattern 1 is selected. when vertical_cursor_position = 0x0fff, the vertical cursor operates in an automatic mode in which its position advances every fram e. in this mode the cursor starts at the column associated with x_addr_start = 0 and advances by a step-size of 8 columns each frame until it reaches the column associated with x_addr_start = 2040, after which it wraps (256 steps). note that the active pixel array is smaller than this, so in the last 56 steps the cursor will not be visible. the wi dth and color of the cursor in this automatic mode are controlled in the usual way. the effect of enabling the test cursors when the image_orientation register is non-zero is not defined by the smia specification. th e behavior of the MT9D014 is shown in figure 22 on page 49. in this figure the test cu rsors are shown as translucent for clarity. in practice, they are opaque (they overlay the imaged scene). the manner in which the test cursors are affected by the value of imag e_orientation can be understood from the following implementation details: ? the test cursors are inserted early in the da ta path, so that they correlate to rows and to columns of the physical pixel array (rat her than to x and to y coordinates of the output image). ? the drawing of a cursor starts when the pixel array row or column address matches the value of the associated cursor_position re gister. as a result, the cursor start posi- tion remains fixed relative to the rows and columns of the pixel array for all settings of image_orientation. ? the cursor generation continues until the appropriate cursor_width pixels have been drawn. the cursor width is generated from the start position and proceeds in the direction of pixel array readout. as a result , each cursor is reflected about an axis corresponding to its start position when the appropriate bit is set in the image_orientation register.
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 49 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor sensor core digital data path preliminary figure 22: test cursor behavior when image_orientation digital gain integer digital gains in the range 1?7 can be programmed. a digital gain of ?0? sets all pixel values to ?0? (the pixel data will simply represent the value applied by the pedestal block). pedestal this block adds the value from r0x0008-9 (d ata_pedestal_) to the incoming pixel value. the data_pedestal register is read-only by default but can be made read/write by clearing the lock_reg bit in r0x301a?b. the only way to disable the effect of the pedestal is to set it to ?0.? readout direction vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 1 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 1 readout direction readout direction readout direction
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 50 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor digital data path preliminary digital data path the digital data path after the sensor core is shown in figure 23. figure 23: data path scaler output buffer limiter compression registers embedded data serial pixel data interface interface with sensor_core
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 51 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor timing specifications preliminary timing specifications power-up specifications the digital and analog supply voltages can be powered up in any order. however, aptina recommends the following power-up sequence to minimize current consumption. the power-up sequence corresponds to the requ irements described in section 3.2 of the smia functional specification. power-up sequence the recommended power-up sequence for the MT9D014 is shown in figure 24 and table 12 on page 52. the available power supplies?v dd , v dd _pll, v aa , vaa_pix?can be turned on at any point or have the sepa ration specified below for reducing current consumption during power-up sequence. 1. turn on the v dd power supply. 2. after 1?500ms, turn on v dd _pll and v aa /vaa_pix power supplies. 3. after the last power supply is stable, enable extclk. 4. assert reset_bar for at least 1ms. 5. wait 2400 extclks for internal initialization into soft standby. 6. configure pll, output, and image settings to desired values. 7. set mode_select = 1 (r0x0100). 8. wait 6750 extclks for the pll to lock before streaming state is reached (enforced in hardware). figure 24: power-up sequence v dd v dd _pll v aa , vaa_pix extclk reset_bar internal init hard reset software standby pll lock streaming t 1 t 2 t 3 t 4 t 5
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 52 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor timing specifications preliminary power-down specification the digital and analog supply voltages can be powered down in any order. however, aptina recommends the following power-down sequence to minimize current consumption. the power-down sequence corresponds to the requirements described in section 3.2 of the smia functional specification. power-down sequence the recommended power-down sequence for the MT9D014 is shown in figure 25 and in table 13 on page 53. the available power supplies?v dd , v dd _pll, vaa, vaa_pix?can be turned off at any point or have the sepa ration specified below for reducing current consumption during power-down sequence. 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. assert hard reset by setti ng reset_bar to a logic ?0.? 4. turn off the v aa /vaa_pix and v dd _pll power supplies. 5. after 1 ? 500ms, turn off v dd and power supply. figure 25: power-down sequence table 12: power-up sequence definition symbol min typ max unit v dd to v dd _pll time t 1 0 C 500 ms v dd to v aa /vaa_pix time t 2 0 C 500 ms active hard reset t 3 1CC ms internal initialization t 4 2400 C C extclks pll lock time t 5 6750 C C extclks v dd_ io v dd, v dd_ ccp v dd _pll v aa , vaa _ pix extclk reset_bar turning off power supplies hard reset software standby streaming t 4 t 3 t 2 t 1
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 53 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor timing specifications preliminary table 13: power-down sequence definition symbol min typ max unit hard reset t 1 1CCms v dd /v aa /vaa_pix to v dd time t 20C500ms v dd _pll to v dd time t 30C500ms
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 54 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor timing specifications preliminary hard standby and hard reset the hard standby state is reached by the as sertion of the reset_bar pad (hard reset). register values are not retained by this action, and will be returned to their default values once hard reset is completed. the minimum power consumption is achieved by the hard standby state. this operating mode complies with section 3.1 of the smia func- tional specification. soft standby and soft reset the MT9D014 can reduce power consumption by switching to the soft standby state when the output is not needed. register valu es are retained in the soft standby state. once this state is reached, soft reset can be optionally enabled to return all register values back to the default. the details of the sequence are shown in figure 26. soft standby 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. soft reset 1. follow the soft standby sequence list. 2. set software_reset = 1 (r0x0103) to start the internal initialization sequence. 3. after 700 extclks, the internal initializa tion sequence is comp leted and the current state returns to soft standby automatically. all registers, including software_reset, returns to their default values. figure 26: soft standby and soft reset extclk mode_select r0x0100 software_reset r0x0103 logic 1 logic 0 streaming soft standby soft reset soft stan dby next row/frame logic 0 logic 1 logic 0 tbd 700 extclks
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 55 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor electrical specifications preliminary electrical specifications extclk the electrical characteristics of the extclk input are shown in table 14. the extclk input supports an ac-coupled sine-wave input clock or a dc-coupled square-wave input clock. table 14: electrical characteristics (extclk) notes: 1. 6750 extclk cycles or 1ms, whichever is smaller. two-wire serial register interface the electrical characteristics of the two- wire serial register interface (sclk, s data ) are shown in table 15. the sclk and s data signals feature fail-s afe input protection, schmitt trigger input, and suppression of input pulses of less than 50ns. definition condition symbol min typ max unit input clock frequency f extclk 6 16 27 mhz input clock period t extclk 166.7 62.5 37 ns input clock amplitude (ac coupled sine wave) external coupling cap value 50C100pf v in _ac 0.5 1.0 1.2 v pp input clock duty cycle 45 50 55 % input clock jitter t jitter 300 ps pll vco lock time t lock 6750 1 extclk cycles input pad capacitance 2.5 pf input high leakage current v in = v dd i ih C10 C 10 ?a input low leakage current v in = d gnd i il C10 C 10 ?a input high voltage (dc coupled) v ih 1.0 C 2.9 v input low voltage (dc coupled) at specified i il v il C0.5 C 0.3 x v dd v table 15: two-wire serial register interface electrical characteristics definition condition symbol min typ max unit input high voltage v ih 0.7 x v dd Cv dd + 0.5 v input low voltage v il C0.5 C 0.3 x v dd v input leakage current no pull-up resistor; v in = v dd or d gnd i in CC 10 ?a output low voltage at specified i ol v ol CC 0.4 v output low current at specified v ol i ol 8.9 C 18.5 ma tri-state output leakage current i o zCC 1 ?a input pad capacitance c in CC 6 pf load capacitance c load CC 15 pf
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 56 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor electrical specifications preliminary serial pixel data interface the electrical characteristics of the serial pixel data interface (clk_p, clk_n, data_p, and data_n) are shown in table 16 control interface the electrical characteristics of the cont rol interface (reset_bar, test, gpi0, gpi1, gpi2, and gpi3) are shown in table 17. table 16: electrical characteristics (serial pixel data interface) v dd = 1.8v; v aa = 2.8v; vaa_pix = 2.8v; v dd _pll = 2.8v; ambient temperature definition symbol min typ max unit operating frequency 180 C 360 mhz fixed common mode voltage v cmf 0.8 0.9 1 v differential voltage swing v od 100 150 200 mv drive current range 0.83 1.5 2 ma drive current variation C C 15 % output impedance 40 C 140 output impedance mismatch C C 10 % clock duty cycle at 416 mhz 45 50 55 % rise time (20C80%) v od 300 C 400 ps fall time (20C80%) v od 300 C 400 ps differential skew C C 500 ps channel-to-channel slew C C 200 ps maximum data rate data/strobe mode data/clock mode CC 640 208 mb/s power supply rejection ratio (psrr) 0C100 mhz 30 C C db power supply rejection ratio (psrr) 100C1000 mhz 10 C C db table 17: electrical characteristics (control interface) definition condition symbol min typ max unit input high voltage v ih 0.7 x v dd Cv aa v input low voltage v il C0.3 C 0.3 x v dd v input leakage current no pull-up resistor; v in = v dd or d gnd i in CC 10 ?a input pad capacitance c in C6.5 C pf
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 57 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor electrical specifications preliminary power-on reset figure 27: internal power-on reset table 18: power-on reset characteristics definition condition symbol min typ max unit v dd rising, crossing v trig _ rising ; internal reset being released t 171015?s v dd falling, crossing v trig _ falling ; internal reset active t 2C0.51?s minimum v dd spike width below v trig _ falling ; considered to be a reset when por cell output is high t 3C0.5C?s minimum v dd spike width below v trig _f alling ; considered to be a reset when por cell output is low t 4C0.5C?s minimum v dd spike width above v trig _ rising ; considered to be a stable supply when por cell output is low while the por cell output is low, all v dd spikes above v trig _ rising less than t 5 must be ignored t 5C1Cns v dd rising trigger voltage v trig _ rising 1.15 C 1.55 v v dd falling trigger voltage v trig _ falling 1.0 C 1.45 v v dd por cell output t 1 t 0 < t 4 > t 2 < t 5 > t 5 < t 0 v trig _ rising v trig _ falling 10% t 3 t 1 90% * *
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 58 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor electrical specifications preliminary operating voltages v aa and vaa_pix must be at the same potential for correct operation of the MT9D014. table 19: dc electrical definitions and characteristics v dd = 1.8v; v aa = 2.8v; vaa_pix = 2.8v; v dd _pll = 2.8v; junction temperature = 70c, 30 fps; dark lighting conditions definition condition symbol min typ max unit v dd v dd 1.7 1.8 1.9 v v aa v aa 2.4 2.8 2.9 v vaa_pix vaa_pix 2.4 2.8 2.9 v v dd _pll v dd _pll 2.4 2.8 2.9 v digital operating current (i dd ) streaming, full resolution i dig 42 65 ma analog operating current (i aa + iaa_pix + i dd _pll) streaming, full resolution i ana 51 80 ma hard standby analog 1 5 ?a digital 1 10 ?a soft standby (clock off) analog 2 10 ?a digital 80 150 ?a soft standby (clock on (6 mhz)) analog 4 10 ?a digital 270 400 ?a
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 59 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor electrical specifications preliminary absolute maximum ratings caution stresses greater than those listed in table 20 may cause permanent damage to the device. expo- sure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. smia specification reference the part itself and this documentation is based on the following smia reference docu- ments: ?functional specification: smia 1.0 part 1: functional specificat ion (version 1.0 dated 30-june-2004) smia 1.0 part 1: functional specificatio n ecr0001 (version 1.0 dated 11-feb-2005) ?electrical specification smia 1.0 part 2: ccp2 specification (version 1.0 dated 30-june-2004) smia 1.0 part 2: ccp2 specification ec r0002 (version 1.0 dated 11-feb-2005) table 20: absolute maximum values definition condition symbol min max unit core digital voltage v dd _ max C0.3 2.2 v analog voltage v aa _ max C0.3 3.2 v pixel supply voltage vaa_pix_ max C0.3 3.2 v pll supply voltage v dd _pll_ max C0.3 3.2 v input high voltage v ih _ max 0.7 x v dd v aa + 0.3 v input low voltage v ih _ max C0.3 0.3 x v dd v operating temperature measure at junction t op C30 70 c storage temperature t stg C40 125 c
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 60 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor revision history preliminary revision history rev. j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/25/10 ? updated to non-confidential rev. h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/4/10 ? update to aptina template rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/20/08 ? added ?embedded data format and control? on page 15 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/10/08 ? update active imager size in table 1, ?key performance parameters,? on page 1 rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/27/08 ? added "power-up sequence" on page 51 ? added figure 24: ?power-up sequence,? on page 51 ? added table 12, ?power-up sequence,? on page 52 ? added "power-down sequence" on page 52 ? added figure 25: ?power-down sequence,? on page 52 ? added table 13, ?power-down sequence,? on page 53 rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/17/08 ? update table 14, ?electrical char acteristics (extclk),? on page 55 ? update table 15, ?two-wire serial register interface electrical characteristics,? on page 55 ? update table 16, ?electrical characteristics (serial pixel data interface),? on page 56 ? update table 17, ?electrical characteri stics (control interface),? on page 56 ? update table 19, ?dc electrical defini tions and characteristics,? on page 58 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/20/07 ? update "shading correction (sc)" on page 37 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/30/07 ? update table 1, ?key performance parameters,? on page 1 ? update figure 2: ?pixel color pattern detail (top right corner),? on page 7 ? update table 6, ?register list and defaul t values?smia configuration,? on page 1 ? update table 7, ?register list and default values?smia parameter limits,? on page 3 ? update table 8, ?register list and default values?manufacturer-specific,? on page 6 ? update table 9, ?register descriptio ns?smia configuration,? on page 8 ? update table 10, ?register descriptions?smia parameter limits,? on page 13 ? update table 11, ?register descriptions?manufacturer-specific,? on page 17 ? update table 5, ?definitions for programming rules,? on page 21 ? update "power-on reset sequence" on page 29 ? update "profile 0 behavior" on page 32 ? update note in figure 13: ?MT9D014 smia profile 1/2 clocking structure,? on page 33 ? update note in figure 14: ?MT9D014 smia profile 0 clocking structure,? on page 34 ? update "programming restrictions when subsampling" on page 40 ? update "hard standby and hard reset" on page 54 ? remove ?hard standby and hard reset? figure ? add "extclk" on page 55
10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, digitalclarity, osmium, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. preliminary: this data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. MT9D014: 1/4-inch 2mp cmos digital image sensor revision history pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 61 ?2007 aptina imaging corporation all rights reserved. preliminary ? add table 14, ?electrical characteristics (extclk),? on page 55 ? update table 15, ?two-wire serial register interface electrical characteristics,? on page 55 ? update table , ?vdd = 1.8v; vaa = 2.8v; vaa_pix = 2.8v; vdd_pll = 2.8v; ambient temperature,? on page 56 ? update table 17, ?electrical characteri stics (control interface),? on page 56 ? update table 18, ?power-on rese t characteristics,? on page 57 ? update table 19, ?dc electrical defini tions and characteristics,? on page 58 ? update table 20, ?absolute maximum values,? on page 59 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/19/07 ?initial release

?products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by aptin a without notice. products are only warranted by aptina to meet aptinas production data sheet specifications. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary ? pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. MT9D014_ds - rev. j 5/10 en 1 ?2007 aptina imaging corporation all rights reserved. 1/4-inch 2mp cmos digital image sensor MT9D014 for the latest data sheet, refer to aptinas web site: www.aptina.com features ? digitalclarity ? cmos imaging technology ?low dark current ? simple two-wire serial interface ? auto black level calibration ? programmable controls: gain, frame size/rate, exposure, left?right and top?bottom image reversal, window size and panning ? data interface: ccp2 compliant sub-low-voltage differential signalling (sub-lvds) ?smia-compatible ? on-chip phase-locked loop (pll) oscillator ? bayer-pattern down-size scaler ? integrated lens shading correction ? superior low-light performance ? internal power switch for ultra-low standby current consumption ? 30 fps at full resolution applications ? cellular phones ? digital still cameras ?pc cameras ?pdas general description the aptina imaging MT9D014 is a 1/4-inch uxga-for- mat cmos active-pixel digital image sensor with a pixel array of 1600h x 1200v (1608h x 1208v including border pixels). it incorpo- rates sophisticated on-chip camera functions such as windowing, mirroring, column and subsampling modes. it is programmable through a simple two-wire serial interface and has very low power consumption. ordering information table 2: available part numbers table 1: key performance parameters parameter value optical format 1/4-inch uxga (4:3) active imager size 3.538mm(h) x 2.658mm(v) 4.425mm diagonal active pixels 1608h x 1208v pixel size 2.2 x 2.2 m color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) maximum data rate 640 mb/s at ccp2 interface frame rate uxga (1600 x 1200) programmable up to 24.04 fps in profile 0 mode (raw10) programmable up to 30.05 fps in profile 1/2 mode (raw10) xga (1024 x 768) programmable up to 75.18 fps in profile 0 mode (raw10) programmable up to 93.98 fps in profile 1/2 mode (raw10) adc resolution 10-bit, on-chip (61db) responsivity 1.38 v/lux-sec dynamic range 68.3b snr max 38.72db supply voltage analog 2.40C2.90v (2.80v nominal) digital 1.70C1.90v (1.80v nominal) power consumption 220mw at 30 fps (typ) operating temperature C30c to +70c packaging bare die part number description MT9D014d00stc c15bc1 bare die
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. MT9D014_ds - rev.j 5/10 en 2 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor table of contents preliminary table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pixel array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 camera module integrator identification procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 two-wire serial register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 start condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 slave address/data direction byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 single read from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 single read from current location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 sequential read, start from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 sequential read, start from current location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 sequential write, start at random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 embedded data format and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 programming restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 output size restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 effect of scaler on legal range of output sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 effect of ccp2 class on legal range of ou tput sizes/frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 output data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 changing registers while streaming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 control of the signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 serial register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 default power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 serial pixel data interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 system states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 power-on reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 soft reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 general purpose inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 streaming/standby control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 profile 0 behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 programming the pll divisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 influence of ccp_data_format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 influence of ccp2_signalling_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 shading correction (sc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 the correction function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 image acquisition modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. MT9D014_ds - rev.j 5/10 en 3 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor table of contents preliminary window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 pixel border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 horizontal mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 vertical flip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 integration time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 analog gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 using per-color or global gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 smia gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 aptina imaging gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 gain code mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 sensor core digital data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 solid color test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 100 percent color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 fade-to-gray color bars test pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 pn9 link integrity pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 test cursors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 pedestal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 digital data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 power-up specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 power-down specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 power-down sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 hard standby and hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 soft standby and soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 soft standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 extclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 two-wire serial register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 serial pixel data interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 operating voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 smia specification reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 4 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor list of figures preliminary list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: pixel color pattern detail (top ri ght corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration: serial pixel data interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: single read from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 5: single read from current locati on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: single write to random location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: sequential write, start at random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: effect of limiter on the smia da ta path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 11: timing of smia data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 12: MT9D014 system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 13: MT9D014 smia profile 1/ 2 clocking structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 14: MT9D014 smia profile 0 clocking structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 15: effect of horizontal_mirror on readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 16: effect of vertic al_flip on readout order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 17: effect of x_odd_inc = 3 on readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 18: pixel readout (no subsampling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 19: pixel readout (x_odd_inc = 3, y_o dd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 20: 100 percent color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 21: fade-to-gray color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 22: test cursor behavior when imag e_orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 23: data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 24: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 25: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 26: soft standby and soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 27: internal power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 5 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor list of tables preliminary list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4: embedded data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 5: definitions for programming rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 6: programming rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7: pll in system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 8: signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 9: streaming/standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 10: row address sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 11: test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 12: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 13: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 14: electrical characterist ics (extclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 15: two-wire serial register interface electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 16: electrical characteristics (serial pixel data interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 17: electrical characteristic s (control interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 18: power-on reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 19: dc electrical definitions and char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 20: absolute maximum values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 6 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor general description preliminary general description the MT9D014 digital image sensor features digitalclarity?aptina?s breakthrough low noise cmos imaging technology that achi eves near-ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. when operated in its default mode, the se nsor generates a uxga image at 24.04 frames per second (fps) when ext_clk_freq_mhz = 16 mhz. an on-chip analog-to-digital converter (adc) generates a 10-bit value for each pixel. functional overview the MT9D014 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single master input clock running between 6 and 27 mhz. the maximum pixel rate is 80 mp/s, corresponding to a vide o timing pixel clock rate of 80 mhz. a block diagram of the sensor is shown in figure 1. figure 1: block diagram the core of the sensor is a 2mp active-pix el array. the timing and control circuitry sequences through the rows of the array, rese tting and then reading each row in turn. in the time interval between resetting a row and re ading that row, the pixels in the row inte- grate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chai n (providing offset correction and gain), and then through an adc. the output from the adc is a 10-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data corrections and applies digital gain). the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels are used to provide data for on-chip offset-correction algorithms (black level control). the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. active-pixel sensor (aps) array analog processing adc scaler limiter shading correction fifo timing control control registers data out two-wire serial interface sync signals
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 7 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor functional overview preliminary the output from the sensor is a bayer pattern ; alternate rows are a sequence of either green and red pixels or blue and green pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. the control registers, timing and control, and digital processing functions shown in figure 1 on page 6 are partitioned into three logical parts: ? a sensor core that provides arra y control and data path corrections. ? a digital shading correction block to comp ensate for color/brightness shading intro- duced by the lens or cra curve mismatch. ? functionality to support the smia standard . this includes a horizontal and vertical image scaler, a limiter, a data compress or, an output fifo, and a serializer. the output fifo prevents data bursts by keeping the data rate continuous. program- mable slew rates are also available to reduce the effect of electromagnetic interference from the output interface. pixel array the sensor core uses a bayer color pattern, as shown in figure 2. the even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. even-numbered columns contain green and blue pixels; odd-numbered columns contain red and green pixels. figure 2: pixel color pattern detail (top right corner) black pixels column readout direction . . . ... row readout direction gr b gr b r gb r gb gr b gr b r gb r gb gr b gr b first clear pixel
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 8 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor operating modes preliminary operating modes the MT9D014 is a smia-compatible sensor wi th a ccp2 interface output data path as defined by smia. for low-noise operation, the MT9D014 requires separate power supplies for analog and digital. incoming digital and analog ground co nductors can be tied together next to the die. both power supply rails should be decoupled from ground using capacitors as close as possible to the die. the use of inductance filters is not recommended on the power supplies or output signals. figure 3: typical configuration: serial pixel data interface notes: 1. all power supplies should be adequately decoupled. 2. aptina recommends a resistor value of 1.5k , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level at all times. 4. test1 must be tied to gnd. test2 must be tied to v dd . 5. also referred to as xshutdown. 6. the gpi pins can be statically pulled high or low and used as module ids, or they can be programmed to perform special functions (s addr , standby) and be dynamically controlled. after reset, these pads are powered up (enabled). failure to bond as required will result in excessive power consumption. 7. aptina recommends that 0.1?f and 1?f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on layout and design considerations. v dd v aa a gnd d gnd s data sclk reset _bar 5 extclk gpi [3 :0] data_n data_p clk_n clk_p to controller external clock in (6-27 mhz) active low reset two - wire serial interface analog power 1 r pull -up test1 1. 5k 2 1.5k 2,3 general purpose inputs test2 v aa v dd 6 atest1 atest2 no connect x x v dd_ pll vaa _ pix digital power 1 vaa_pix v dd _pll
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 9 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor camera module integrator identification procedure preliminary camera module integrator identification procedure see MT9D014 developer guide.
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 10 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor signal descriptions preliminary signal descriptions table 3 provides signal descriptions for MT9D014 die. for pad location and aperture information, refer to the MT9D014 die data sheet. table 3: signal descriptions pad name pad type description extclk input master clock input. pll input clock. 6C27 mhz. reset_bar (xshutdown) input asynchronous active low reset. when asserted, data output stops and all internal registers are restored to their factory default settings. sclk input serial clock for access to control and status registers. gpi[3:0] input general purpose inputs. after reset, these pads are powered up (enabledsee r0x301a) by default; these pads must be bonded to a high or low state. any of these pads can be configured to provide hardware control of the standby, output enable, and shutter trigger functions. failure to bond as required will result in excessive power consumption. test1 input enable manufacturing test modes. wire to digital gnd for functional operation. test2 input tie high for normal operation. s data i/o serial data for reads from and writes to control and status registers. data_p output differential ccp2 (sub_lvds) serial data (positive). data_n output differential ccp2 (sub_lvds) serial data (negative). clk_p output differential ccp2 (sub_lvds) serial clock/strobe (positive). clk_n output differential ccp2 (sub_lvds) serial clock/strobe (negative). v aa supply analog power supply. v dd _pll supply pll power supply. vaa_pix supply analog power supply. a gnd supply analog ground. v dd supply digital power supply. d gnd supply digital ground.
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 11 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor two-wire serial register interface preliminary two-wire serial register interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the sensor. this interface is desi gned to be compatible with the smia 1.0 part 2: ccp2 specification camera control interfac e (cci), which uses the electrical charac- teristics and transfer protocols of the i 2 c specification. the protocols described in the i 2 c specification allow the slave device to driv e sclk low; the sensor uses sclk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial inte rface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both sclk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while sclk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the mt9d0 14 are 0x20 (write address) and 0x21 (read address) in accordance with the smia specif ication. alternate slav e addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the s addr signal through the gpi pad. an alternate slave address can al so be programmed through r0x31fc. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the sclk clock period following the data transfer . the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when sclk is low and must be stable while sclk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the sclk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence.
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 12 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor two-wire serial register interface preliminary message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. the protocol used is outside the scope of the smia cci. stop condition a stop condition is defined as a low-to-high transition on s data while sclk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each sclk clock period. s data can change when sclk is low and must be stable while sclk is high. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the mast er generates an acknowledge bit after each 8-bit transfer. the slave?s internal register address is automatically incremented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 13 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor two-wire serial register interface preliminary single read from random location this sequence (figure 4) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates th e write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out 1 byte of register data. the master terminates the read by generating a no-acknowledge bit followed by a stop condition. figure 4 sh ows how the internal register address main- tained by the MT9D014 is loaded and incremented as the sequence proceeds. figure 4: single read from random location single read from current location this sequence (figure 5) performs a read using the current value of the MT9D014 internal register address. the master terminates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 5: single read from current location sequential read, start from random location this sequence (figure 6) starts in the same way as the single read from random loca- tion (figure 4). instead of generating a no-ackno wledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until l by tes have been read. figure 6: sequential read, start from random location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p aa a a
pdf: 0526161444/source: 6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 14 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor two-wire serial register interface preliminary sequential read, start from current location this sequence (figure 7) starts in the same wa y as the single read from current location (figure 5 on page 13). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master gene rates an acknowledge bit and continues to perform byte reads until l bytes have been read. figure 7: sequential read, start from current location single write to random location this sequence (figure 8) begins with the mast er generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 8: single write to random location sequential write, start at random location this sequence (figure 9) starts in the same way as the single write to random location (figure 8). instead of generating a stop cond ition after the first byte of data has been transferred, the master continue s to perform byte writes until l bytes have been written. the write is terminated by the ma ster generating a stop condition. figure 9: sequential write, start at random location read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 15 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor embedded data format and control preliminary embedded data format and control when the serial pixel data path is selected, the first two rows of the output image contain register values that are appropriate for the im age. in this mode, the first two lines and the last line of data are not equally spaced. the fo rmat of this data is shown in table 4. in the table, 8-bit (raw8) and 10-bit (raw10) versions of the data are shown. the 10-bit format places the data byte in bits [9:2] and sets bits [1:0] to a constant value of 01. register values that are shown as ???? are dynamic and may change from frame to frame. when the parallel pixel data path is selected and r0x306e-f[2:0]=2 (parallel pixel data output mux selects fifo data). the output image contains two rows of embedded data. table 4: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface addr comment 10-bit 8-bit two-wire serial interface addr comment 0 0x029 0x0a 2-byte tagged data format (embedded data) 0x029 0x0a start of embedded data line 1 0x2a9 0xaa cci register index msb 0x2a9 0xaa cci register index msb 2 0x001 0x00 address 00xx 0x005 0x01 address 01xx 3 0x295 0xa5 cci register index lsb 0x295 0xa5 cci register index lsb 4 0x001 0x00 address xx00 0x081 0x20 address xx20 5 0x169 0x5a auto increment 0x169 0x5a auto increment 6 0x059 0x16 0000 model_id hi 0x001 0x00 120 gain mode 7 0x169 0x5a 0x2a9 0xaa cci register index msb 8 0x001 0x00 0001 model_id lo 0x009 0x02 address 02xx 9 0x169 0x5a 0x295 0xa5 cci register index lsb 10 0x001 0x00 0002 revision_number 0x001 0x00 address xx00 11 0x169 0x5a 0x169 0x5a auto increment 12 0x019 0x06 0003 manufacturer_id ?? ?? 0200 fine_integration_time hi 13 0x169 0x5a 0x169 0x5a 14 0x029 0x0a 0004 smia_version ?? ?? 0201 fine_integration_time lo 15 0x169 0x5a 0x169 0x5a 16 ?? ?? 0005 frame_count ?? ?? 0202 coarse_integration_time hi 17 0x169 0x5a 0x169 0x5a 18 ?? ?? 0006 pixel_order ?? ?? 0203 coarse_integration_time lo 19 0x2a9 0xaa cci register index msb 0x169 0x5a 20 0x001 0x00 address 00xx ?? ?? 0204 analogue_gain_code_global hi 21 0x295 0xa5 cci register index lsb 0x169 0x5a 22 0x021 0x08 address xx08 ?? ?? 0205 analogue_gain_code_global lo 23 0x169 0x5a auto increment 0x169 0x5a 24 ?? ?? 0008 data_pedestal_hi ?? ?? 0206 analogue_gain_code_greenr hi 25 0x169 0x5a 0x169 0x5a 26 ?? ?? 0009 data_pedestal lo ?? ?? 0207 analogue_gain_code_greenr lo 27 0x2a9 0xaa cci register index msb 0x169 0x5a 28 0x001 0x00 address 00xx ?? ?? 0208 analogue_gain_code_red hi 29 0x295 0xa5 cci register index lsb 0x169 0x5a 30 0x101 0x40 address xx40 ?? ?? 0209 analogue_gain_code_red lo 31 0x169 0x5a auto increment 0x169 0x5a
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 16 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor embedded data format and control preliminary 32 0x005 0x01 0040 frame_format_model_type ?? ?? 020a analogue_gain_code_blue hi 33 0x169 0x5a 0x169 0x5a 34 0x049 0x12 0041 frame_format_model_subtype ?? ?? 020b analogue_gain_code_blue lo 35 0x169 0x5a 0x169 0x5a 36 ?? ?? 0042 frame_format_descriptor_0 hi ?? ?? 020c analogue_gain_code_greenb hi 37 0x169 0x5a 0x169 0x5a 38 ?? ?? 0043 frame_format_descriptor_0 lo ?? ?? 020d analogue_gain_codegreenb lo 39 0x169 0x5a 0x169 0x5a 40 ?? ?? 0044 frame_format_descriptor_1 hi ?? ?? 020e digital_gain_greenr hi 41 0x169 0x5a 0x169 0x5a 42 ?? ?? 0045 frame_format_descriptor_1 lo ?? ?? 020f digital_gain_greenr lo 43 0x169 0x5a 0x169 0x5a 44 ?? ?? 0046 frame_format_descriptor _2 hi ?? ?? 0210 digital_gain_red hi 45 0x169 0x5a 0x169 0x5a 46 ?? ?? 0047 frame_format_descriptor_2 lo ?? ?? 0211 digital_gain_red lo 47 0x169 0x5a 0x169 0x5a 48 0x001 0x00 0048 frame_format_descriptor_3 hi ?? ?? 0212 digital_gain_blue hi 49 0x169 0x5a 0x169 0x5a 50 0x001 0x00 0049 frame_format_descriptor_3 lo ?? ?? 0213 digital_gain_blue lo 51 0x169 0x5a 0x169 0x5a 52 0x001 0x00 004a frame_format_descriptor_4 hi ?? ?? 0214 digital_gain_greenb hi 53 0x169 0x5a 0x169 0x5a 54 0x001 0x00 004b frame_format_descriptor_4 lo ?? ?? 0215 digital_gain_greenb lo 55 0x169 0x5a 0x2a9 0xaa cci register index msb 56 0x001 0x00 004c frame_format_descriptor_5 hi 0x00d 0x03 address 03xx 57 0x169 0x5a 0x295 0xa5 cci register index lsb 58 0x001 0x00 004d frame_format_descriptor_5 lo 0x001 0x00 address xx00 59 0x169 0x5a 0x169 0x5a auto increment 60 0x001 0x00 004e frame_format_descriptor_6 hi ?? ?? 0300 vt_pix_clk_div hi 61 0x169 0x5a 0x169 0x5a 62 0x001 0x00 004f frame_format_descriptor_6 lo ?? ?? 0301 vt_pix_clk_div lo 63 0x169 0x5a 0x169 0x5a 64 0x001 0x00 0050 frame_format_descriptor_7 hi ?? ?? 0302 vt_sys_clk_div hi 65 0x169 0x5a 0x169 0x5a 66 0x001 0x00 0051 frame_format_descriptor_7 lo ?? ?? 0303 vt_sys_clk_div lo 67 0x169 0x5a 0x169 0x5a 68 0x001 0x00 0052 frame_format_descriptor_8 hi ?? ?? 0304 pre_pll_clk_div hi 69 0x169 0x5a 0x169 0x5a 70 0x001 0x00 0053 frame_format_descriptor_8 lo ?? ?? 0305 pre_pll_clk_div lo 71 0x169 0x5a 0x169 0x5a 72 0x001 0x00 0054 frame_format_descriptor_9 hi ?? ?? 0306 pll_multiplier_hi 73 0x169 0x5a 0x169 0x5a 74 0x001 0x00 0055 frame_format_descriptor_9 lo ?? ?? 0307 pll_multiplier_lo table 4: embedded data (continued) row 0 row 1 offset 10-bit 8-bit two-wire serial interface addr comment 10-bit 8-bit two-wire serial interface addr comment
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 17 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor embedded data format and control preliminary 75 0x169 0x5a 0x169 0x5a 76 0x001 0x00 0056 frame_format_descriptor_10 hi ?? ?? 0308 op_pix_clk_div hi 77 0x169 0x5a 0x169 0x5a 78 0x001 0x00 0057 frame_format_descriptor_10 lo ?? ?? 0309 op_pix_clk_div lo 79 0x169 0x5a 0x169 0x5a 80 0x001 0x00 0058 frame_format_descriptor_11 hi ?? ?? 030a op_sys_clk_div hi 81 0x169 0x5a 0x169 0x5a 82 0x001 0x00 0059 frame_format_descriptor_11 lo ?? ?? 030b op_sys_clk_div lo 83 0x169 0x5a 0x2a9 0xaa cci register index msb 84 0x001 0x00 005a frame_format_descriptor_12 hi 0x00d 0x03 address 03xx 85 0x169 0x5a 0x295 0x0a5 cci register index lsb 86 0x001 0x00 005b frame_format_descriptor_12 lo 0x101 0x40 address xx40 87 0x169 0x5a 0x169 0x5a auto increment 88 0x001 0x00 005c frame_format_descriptor_13 hi ?? ?? 0340 frame_length_lines hi 89 0x169 0x5a 0x169 0x5a 90 0x001 0x00 005d frame_format_descriptor_13 lo ?? ?? 0341 frame_length_lines lo 91 0x169 0x5a 0x169 0x5a 92 0x001 0x00 005e frame_format_descriptor_14 hi ?? ?? 0342 line_length_pck hi 93 0x169 0x5a 0x169 0x5a 94 0x001 0x00 005f frame_format_descriptor_14 lo ?? ?? 0343 line_length_pck lo 95 0x2a9 0xaa cci register index msb 0x169 0x5a 96 0x001 0x00 address 00xx ?? ?? 0344 x_addr_start hi 97 0x295 0xa5 cci register index lsb 0x169 0x5a 98 0x201 0x80 address xx80 ?? ?? 0345 x_addr_start lo 99 0x169 0x5a auto increment 0x169 0x5a 100 0x001 0x00 0080 analogue_gain_capability hi ?? ?? 0346 y_addr_start hi 101 0x169 0x5a 0x169 0x5a 102 0x005 0x01 0081 analogue_gain_capability lo ?? ?? 0347 y_addr_start lo 103 0x2a9 0xaa cci register index msb 0x169 0x5a 104 0x001 0x00 address 00xx ?? ?? 0348 x_addr_end hi 105 0x295 0xa5 cci register index lsb 0x169 0x5a 106 0x211 0x84 address xx84 ?? ?? 0349 x_addr_end lo 107 0x169 0x5a auto increment 0x169 0x5a 108 0x001 0x00 0084 analogue_gain_code_min hi ?? ?? 034a y_addr_end hi 109 0x169 0x5a 0x169 0x5a 110 0x021 0x08 0085 analogue_gain_code_min lo ?? ?? 034b y_addr_end lo 111 0x169 0x5a 0x169 0x5a 112 0x001 0x00 0086 analogue_gain_code_max hi ?? ?? 034c x_output_size hi 113 0x169 0x5a 0x169 0x5a 114 0x1fd 0x7f 0087 analogue_gain_code_max lo ?? ?? 034d x_output_size lo 115 0x169 0x5a 0x169 0x5a 116 0x001 0x00 0088 analogue_gain_code_step hi ?? ?? 034e y_output_size hi 117 0x169 0x5a 0x169 0x5a table 4: embedded data (continued) row 0 row 1 offset 10-bit 8-bit two-wire serial interface addr comment 10-bit 8-bit two-wire serial interface addr comment
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 18 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor embedded data format and control preliminary 118 0x005 0x01 0089 analogue_gain_code_step lo ?? ?? 034f y_output_size lo 119 0x169 0x5a 0x2a9 0xaa cci register index msb 120 0x001 0x00 008a analogue_gain_type hi 0x00d 0x03 address 03xx 121 0x169 0x5a 0x295 0xa5 cci register index lsb 122 0x001 0x00 008b analogue_gain_type lo 0x201 0x80 address xx80 123 0x169 0x5a 0x169 0x5a auto increment 124 0x001 0x00 008c analogue_gain_m0 lo ?? ?? 0380 x_even_inc hi 125 0x169 0x5a 0x169 0x5a 126 0x005 0x01 008d analogue_gain_m0 lo ?? ?? 0381 x_even_inc lo 127 0x169 0x5a 0x169 0x5a 128 0x001 0x00 008e analogue_gain_c0 lo ?? ?? 0382 y_odd_inc hi 129 0x169 0x5a 0x169 0x5a 130 0x001 0x00 008f analogue_gain_c0 lo ?? ?? 0383 y_odd_inc lo 131 0x169 0x5a 0x169 0x5a 132 0x001 0x00 0090 analogue_gain_m1 lo ?? ?? 0384 y_even_inc hi 133 0x169 0x5a 0x169 0x5a 134 0x001 0x00 0091 analogue_gain_m1 lo ?? ?? 0385 y_even_inc lo 135 0x169 0x5a 0x169 0x5a 136 0x001 0x00 0092 analogue_gain_c1 lo ?? ?? 0386 x_odd_inc hi 137 0x169 0x5a 0x169 0x5a 138 0x021 0x08 0093 analogue_gain_c1 lo ?? ?? 0387 x_odd_inc lo 139 0x2a9 0xaa cci register index msb 0x2a9 0xaa cci register index msb 140 0x001 0x00 address 00xx 0x011 0x04 address 04xx 141 0x295 0xa5 cci register index lsb 0x295 0xa5 cci register index lsb 142 0x301 0xc0 address xxc0 0x001 0x00 address xx00 143 0x169 0x5a auto increment 0x169 0x5a auto increment 144 0x005 0x01 00c0 data_format_model_type ?? ?? 0400 scaling_mode hi 145 0x169 0x5a 0x169 0x5a 146 0x00d 0x03 00c1 data_format_model_subtype ?? ?? 0401 scaling_mode lo 147 0x169 0x5a 0x169 0x5a 148 0x029 0x0a 00c2 data_format_descriptor_0 hi ?? ?? 0402 spatial_sampling hi 149 0x169 0x5a 0x169 0x5a 150 0x029 0x0a 00c3 data_format_descriptor_0 lo ?? ?? 0403 spatial_sampling lo 151 0x169 0x5a 0x169 0x5a 152 0x021 0x08 00c4 data_format_descriptor_1 hi ?? ?? 0404 scale_m hi 153 0x169 0x5a 0x169 0x5a 154 0x021 0x08 00c5 data_format_descriptor_1 lo ?? ?? 0405 scale_m lo 155 0x169 0x5a 0x169 0x5a 156 0x029 0x0a 00c6 data_format_descriptor_2 hi 0x001 0x00 0406 scale_n hi 157 0x169 0x5a 0x169 0x5a 158 0x021 0x08 00c7 data_format_descriptor_2 lo 0x041 0x10 0407 scale_n lo 159 0x169 0x5a 0x2a9 0xaa cci register index msb 160 0x001 0x00 00c8 data_format_descriptor_3 hi 0x015 5 address 05xx table 4: embedded data (continued) row 0 row 1 offset 10-bit 8-bit two-wire serial interface addr comment 10-bit 8-bit two-wire serial interface addr comment
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 19 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor embedded data format and control preliminary 161 0x169 0x5a 0x295 0xa5 cci register index lsb 162 0x001 0x00 00c9 data_format_descriptor_3 lo 0x001 0x00 address xx00 163 0x169 0x5a 0x169 0x5a auto increment 164 0x001 0x00 00ca data_format_descriptor_4 hi 0x001 0x00 0500 compression_mode hi 165 0x169 0x5a 0x169 0x5a 166 0x001 0x00 00cb data_format_descriptor_4 lo 0x005 0x01 0501 compression_mode lo 167 0x169 0x5a 0x2a9 0xaa cci register index msb 168 0x001 0x00 00cc data_format_descriptor_5 hi 0x019 0x06 address 06xx 169 0x169 0x5a 0x295 0xa5 cci register index lsb 170 0x001 0x00 00cd data_format_descriptor_5 lo 0x001 0x00 address xx00 171 0x169 0x5a 0x169 0x5a auto increment 172 0x001 0x00 00ce data_format_descriptor_6 hi ?? ?? 0600 test_pattern_mode hi 173 0x169 0x5a 0x169 0x5a 174 0x001 0x00 00cf data_format_descriptor_6 lo ?? ?? 0601 test_pattern_mode lo 175 0x2a9 0xaa cci register index msb 0x169 0x5a 176 0x005 0x01 address 01xx ?? ?? 0602 test_data_red hi 177 0x295 0xa5 cci register index lsb 0x169 0x5a 178 0x001 0x00 address xx00 ?? ?? 0603 test_data_red lo 179 0x169 0x5a auto increment 0x169 0x5a 180 ?? ?? 0100 mode_select ?? ?? 0604 test_data_greenr hi 181 0x169 ?? 0x169 0x5a 182 ?? 0x00 0101 image_orientation ?? ?? 0605 test_data_greenr lo 183 0x2a9 0xaa cci register index msb 0x169 0x5a 184 0x005 0x01 address 01xx ?? ?? 0606 test_data_blue hi 185 0x295 0xa5 cci register index lsb 0x169 0x5a 186 0x00d 0x03 address xx03 ?? ?? 0607 test_data_blue lo 187 0x169 0x5a auto increment 0x169 0x5a 188 0x001 0x00 0103 software_reset ?? ?? 0608 test_data_greenb hi 189 0x169 0x5a 0x169 0x5a 190 ?? ?? 0104 grouped_parameter_hold ?? ?? 0609 test_data_greenb lo 191 0x169 0x5a 0x169 0x5a 192 ?? ?? 0105 mask_corrupted_frames ?? ?? 060a horizontal_cursor_width hi 193 0x2a9 0xaa cci register index msb 0x169 0x5a 194 0x005 0x01 address 01xx ?? ?? 060b horizontal_cursor_width lo 195 0x295 0xa5 cci register index lsb 0x169 0x5a 196 0x041 0x10 address xx10 ?? ?? 060 c horizontal_cursor_position hi 197 0x169 0x5a auto increment 0x169 0x5a 198 ?? ?? 0110 ccp2_channel_identifier ?? ?? 060d horizontal_cursor_position lo 199 0x169 0x5a 0x169 0x5a 200 ?? ?? 0111 ccp2_signalling_mode ?? ?? 060e vertical_cursor_width hi 201 0x169 0x5a 0x169 0x5a 202 ?? ?? 0112 ccp_data_format hi ?? ?? 060f vertical_cursor_width lo 203 0x169 0x5a 0x169 0x5a table 4: embedded data (continued) row 0 row 1 offset 10-bit 8-bit two-wire serial interface addr comment 10-bit 8-bit two-wire serial interface addr comment
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 20 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor embedded data format and control preliminary 204 ?? ?? 0113 ccp_data_format lo ?? ?? 0610 vertical_cursor_position hi 205 0x01d 0x07 null data 0x169 0x5a 206 0x01d 0x07 null data - up to end-of-line ?? ?? 0611 vertical_cursor_position lo 207 0x01d 0x07 null data 208 0x01d 0x07 null data - up to end-of-line table 4: embedded data (continued) row 0 row 1 offset 10-bit 8-bit two-wire serial interface addr comment 10-bit 8-bit two-wire serial interface addr comment
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 21 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor programming restrictions preliminary programming restrictions the smia specification imposes a number of programming restrictions. an implemen- tation naturally imposes additional restrictions. table 5 shows a list of programming rules that must be adhered to for correct operation of the MT9D014. aptina recom- mends that these rules are encoded into the device driver stack?either implicitly or explicitly. table 5: definitions for programming rules name definition xskip xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3 yskip yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3 table 6: programming rules parameter minimum value maximum value origin coarse_integration_time coarse_integration_time_m in frame_length_lines - coarse_integration_time_max_margin smia fine_integration_time fine_integration_time_min line_length_pck - fine_integration_time_max_margin smia digital_gain_* digital_gain_min digital_gain_max smia digital_gain_* is an integer multiple of digital_gain_step_size smia frame_length_lines min_frame_length_lines max_frame_length_lines smia line_length_pck line_length_pck min_line_length_pck max_line_length_pck smia ((x_addr_end - x_addr_start + x_odd_inc)/xskip) + min_line_blanking_pck frame_length_lines ((y_addr_end - y_addr_start + y_odd_inc)/yskip) + min_frame_blanking_lines smia x_addr_start x_addr_min x_addr_max smia x_addr_end x_addr_start x_addr_max smia (x_addr_end - x_addr_start+ x_odd_inc) must be positive must be positive smia x_addr_start[0] 0 0 smia x_addr_end[0] 1 1 smia y_addr_start y_addr_min y_addr_max smia y_addr_end y_addr_start y_addr_max smia (y_addr_end - y_addr_start + y_odd_inc)/ must be positive must be positive smia y_addr_start[0] 0 0 smia y_addr_end[0] 1 1 smia x_even_inc min_even_inc max_even_inc smia x_even_inc[0] 1 1 smia y_even_inc min_even_inc max_even_inc smia y_even_inc[0] 1 1 smia x_odd_inc min_odd_inc max_odd_inc smia x_odd_inc[0] 1 1 smia y_odd_inc min_odd_inc max_odd_inc smia
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 22 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor programming restrictions preliminary notes: 1. with subsampling, start and end pixels must be addressed (impact on x/y start/end addresses, function of image orientation bits). smia fs errata see subsampling on page 39. output size restrictions the smia ccp2 specification imposes the rest riction that an outp ut line shall be a multiple of 32 bits in length. this imposes an additional restriction on the legal values of x_output_size: ? when ccp_format[7:0] = 8 (raw8 data), x_output_size must be a multiple of 4 (x_output_size[1:0] = 0). ? when ccp_format[7:0] = 10 (raw10 data), x_output_size must be a multiple of 16 (x_output_size[3:0] = 0). this restriction can be met by rounding up x_output_size to an appropriate multiple. any extra pixels in the output image as a resu lt of this rounding contain undefined pixel data but are guaranteed not to cause false synchronization on the ccp2 data stream. there is an additional restriction that x_outp ut_size must be small enough such that the output row time (set by x_output_size, the framing and crc overhead of 12 bytes, the ccp_signalling_mode and the ou tput clock rate) must be less than the row time of the video array (set by line_length_pc k and the video timing clock rate). effect of scaler on legal range of output sizes when the scaler is enabled, it is necessary to adjust the values of x_output_size and y_output_size to match the image size gene rated by the scaler. the MT9D014 will not operate properly if the x_output_size and y_ou tput_size are significantly larger than the y_odd_inc[0] 1 1 smia scale_m scaler_m_min scaler_m_max smia scale_n scaler_n_min scaler_n_max smia x_output_size 256 1608 minimum from smia fs section 5.2.2.5. maximum is a consequence of the output fifo size on this implementation. x_output_size[0] 0 (this is enforced in hardware: bit[0] is read- only) 0 smia fs section 5.2.2.2. y_output_size 2 frame_length_lines minimum ensures 1 bayer row-pair. maximum avoids output frame being longer than pixel array frame. y_output_size[0] 0 (this is enforced in hardware: bit[0] is read- only) 0 smia fs section 5.2.2.2 table 6: programming rules (continued) parameter minimum value maximum value origin
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 23 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor programming restrictions preliminary output image. to understand the reason for this, consider the situation where the sensor is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the number of pixels in each direction). this situation is shown in figure 10. figure 10: effect of limiter on the smia data path in figure 10, three different stages in the smia data path (see ?digital data path? on page 50) are shown. the first stage is the output of the sensor core. the core is running at full resolution and x_output_size is set to match the active array size. the line_valid (lv) signal is asserted once per row and remains asserted for n pixel times. the pixel_valid signal toggles with the same timing as lv, indicating that all pixels in the row are valid. the second stage is the output of the scaler, when the scaler is set to reduce the image size by one-half in each dimension. the effe ct of the scaler is to combine groups of pixels. therefore, the row time remains the same, but only half the pixels out of the scaler are valid. this is signalled by transitions in pixel_valid. overall, pixel_valid is asserted for ( n /2) pixel times per row. the third stage is the output of the limiter when the x_output_size is still set to match the active array size. because the scaler has reduced the amount of valid pixel data without reducing the row time, the limiter attempts to pad the row with ( n /2) additional pixels. if this has the effect of extending lv across th e whole of the horizontal blanking time, the MT9D014 will cease to generate output frames. a correct configuration is shown in figure 11 on page 24, in addition to showing the x_output_size reduced to match the output size of the scaler. in this configuration, the output of the limiter does not extend lv. figure 11 on page 24 also shows the effect of the output fifo, which forms the final stage in the smia data path. the output fifo merges the intermittent pixel data back into a contiguous stream. although not shown in this example, the output fifo is also capable of operating with an output clock that is at a different frequency from its input clock. core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line_valid scaler output: scaled to half size line_valid pixel_valid limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1 line_valid pixel_valid pixel_valid
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 24 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor programming restrictions preliminary figure 11: timing of smia data path effect of ccp2 class on legal range of output sizes/frame rate the pixel array readout rate is set by line_length_pck * frame_length_lines. with the default register values, one frame time ta kes 2184 * 1219 = 2662296 pixel periods. this value includes vertical and horizontal bl anking times so that the full-size image 1600 x 1202 (1200 lines of pixel data, 2 lines of embedded information) forms a subset of these pixels. when the internal clock is running at 64 mh z, this frame time corresponds to 2662296/ 64e6 = 41.60ms, giving rise to a frame rate of 24.04 fps. each pixel is 10 bits, by default. as a result, the serial data rate is required to transmit faster than the pixel rate. however, the smia ccp2 class 2 specifications has a maximum of 650 mb/s, which cannot be exceeded. the smia ccp2 specification shows that cl ass 0 (data/clock) runs up to 208 mb/s. therefore, it is not possible to transmit full-resolution images at 15 fps using ccp2 class 0. changing the ccp_data_format (to use 8 bits per pixel) reduces the bandwidth require- ment, but is not enough to al low full-resolution operation. the only way to get a full image out is to redu ce the pixel clock rate until it is appropriate for the maximum ccp2 class 0 data rate. this requires the pixel rate to be reduced to 20.8 mhz. this has the side effect of reducing the frame rate. repeating the calculation above, at 20.8 mhz internal clock, this co rresponds to 2662296/20.8e6 = 128ms, giving rise to a frame rate of 7.81 fps. to use ccp2 class 0 with an internal clock of 64 mhz, it is necessary to reduce the amount of output data. this can be achieved by changing x_output_size, y_output_size so that less data comes out per frame. a change to the output size can be done in conjunction with windowing the image from the sensor (by adjusting x_addr_start, x_addr_end, y_addr_start, y_addr_end ) or by enabling the scaler. core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line_valid scaler output: scaled to half size line_valid pixel_valid limiter output: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 pixel_valid line_valid pixel_valid output fifo: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 line_valid pixel_valid
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 25 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor programming restrictions preliminary output data timing the output fifo acts as a boundary between two clock domains. data is written to the fifo in the vt (video timing) clock domain. data is read out of the fifo in the op (output) clock domain. when the scaler is disabled, the data rate in the vt clock domain is constant and uniform during the active period of each pi xel array row readout. when the scaler is enabled, the data rate in the vt clock domain becomes intermittent, corresponding to the data reduction performed by the scaler. maximum frame rate is achieved by setting the video timing clock (vt_clk_freq_mhz) to 80 mhz and using the fifo to reduce horizontal blanking data rate to 640 mb/s. at this setting, a maximum frame rate of 30.05 fps can be achieved. a key constraint when configuring the clock fo r the output fifo is that the frame rate out of the fifo must exactly match the frame rate into the fifo. when the scaler is disabled, this constraint can be met by imposi ng the rule that the row time on the ccp2 data stream must be greater than or equal to the row time at the pixel array. the row time on the ccp2 data stream is calculated fr om the x_output_size and the ccp_data_format (8 or 10 bits per pixel), and must include the time taken in the ccp2 data stream for start of frame/row, end of row/ frame and checksum symbols. caution if this constraint is not met, the fifo will either underrun or overrun. fifo underrun or overrun is a fatal error condition that is signalled through the data path_status register (r0x306a). changing registers while streaming the following registers should only be repr ogrammed while the sensor is in software standby: ? ccp2_channel_identifier ? ccp2_signalling_mode ? ccp_data_format ?scale_m ?vt_pix_clk_div ? vt_sys_clk_div ? pre_pll_clk_div ? pll_multiplier ? op_pix_clk_div ?op_sys_clk_div
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 26 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor control of the signal interface preliminary control of the signal interface this section describes the operation of the signal interface in all functional modes. serial register interface the serial register interface uses the following signals: ?sclk ?s data ?s addr (through a gpi pad) sclk is an input-only signal and must always be driven to a valid logic level for correct operation; if the driving device can place this signal in high-z state, an external pull-up resistor should be connected on this signal. s data is a bidirectional signal. an external pull-up resistor should be connected on this signal. s addr is a signal which can be optionally enab led and controlled by a gpi pad to select an alternate slave address. these slave addresses can also be programmed through r0x31fc. this interface is described in detail in ?extclk? on page 55. default power-up state the MT9D014 provides interfaces for pixel data through the ccp2 high-speed serial interface described by the smia specification. at power up and after a hard or soft reset, the reset state of the MT9D014 is to enable the smia ccp2 high-speed serial interface. smia ccp2 requirements and supports both data/clock signalling and data/strobe signalling. the data_p, data_n, clk_p, and clk_n pads are turned off if the smia serial disable bit is asserted (r0x301a?b[12] = 1) or when the sensor is in the soft standby state. in data/clock mode, the clock remains high wh en no data is being transmitted. in data/ strobe mode before frame start, clock is low and data is high.
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 27 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor control of the signal interface preliminary serial pixel data interface the serial pixel data interface uses the following output-only signal pairs: ?data_p ?data_n ?clk_p ?clk_n the signal pairs are driven differentially using sub-lvds switching levels. this interface conforms to the smia ccp2 requirements and supports both data/clock signalling and data/strobe signalling. the data_p, data_n, clk_p, and clk_n pads are turned off if the smia serial disable bit is asserted (r0x301a?b[12] = 1) or when the sensor is in the soft standby state. in data/clock mode, the clock remains high wh en no data is being transmitted. in data/ strobe mode before frame start, clock is low and data is high.
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 28 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor control of the signal interface preliminary system states the system states of the MT9D014 are repr esented as a state diagram in figure 12 and described in subsequent sections. the effect of reset_bar on the system state and the configuration of the pll in the different states are shown in table 7 on page 29. the sensor?s operation is broken down into th ree separate states: hardware standby, soft standby, and streaming. the transition be tween these states might take a certain amount of clock cycles as outlined in table 7. figure 12: MT9D014 system states powered off por active internal init ( 700 extclks ) software standby streaming wait for frame/row end pll lock (6750 extclks) software reset powered on por completed hardware reset released init finished por not yet completed init not completed pll aquiring lock mode_select =1 lock acquired mode_select = 0 frame in progress 1> hardware standby hardware reset active reset transition - 0 (asynchronous from every state ) power supply turned off (asynchronous from every state )
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 29 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor control of the signal interface preliminary notes: 1. vco = voltage-controlled oscillator. power-on reset sequence when power is applied to the MT9D014, it enters a low-power hardware standby state. exit from this state is controlled by the later of two events: 1. the negation of the reset_bar input. 2. a timeout of the internal power-on reset circuit. it is possible to hold reset_bar permanently negated and rely upon the internal power-on reset circuit. when reset_bar is asserted, it asynchronous ly resets the sensor, truncating any frame that is in progress. when the sensor leaves the hardware standb y state, it waits for power-on reset and performs an internal initialization sequence that takes 700 extclk cycles. after this time, it enters a low-power soft standby state. while the initialization sequence is in progress, the MT9D014 will not respond to re ad transactions on its two-wire serial interface. therefore, a method to determine when the initialization sequence has completed is to poll a sensor register; for example, r0x0000. while the initialization sequence is in progress, the sensor will not respond to its device address and reads from the sensor will result in a nack on the two-wire serial interface bus. when the sequence has completed, reads will return the operational value for the register (0x1501 if r0x0000 is read). when the sensor leaves soft standby mode and enables the vco, an internal delay will keep the pll disconnected for up to 6750 extclks so that the pll can lock. soft reset sequence the MT9D014 can be reset under software control by writing ?1? to software_reset (r0x0103). a software reset asynchronously re sets the sensor, truncating any frame that is in progress. the sensor starts the intern al initialization sequence, while the pll and analog blocks are turned off. at this point, the behavior is exactly the same as for the power-on reset sequence. table 7: pll in system states state extclks pll powered off hardware standby por active internal initialization 700 vco powered down software standby pll lock 6750 vco powering up and locking, pll output bypassed streaming vco running, pll output active wait for frame end
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 30 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor control of the signal interface preliminary signal state during reset table 8 shows the state of the signal inte rface during hardware standby (reset_bar asserted) and the default state during soft st andby (after exit from hardware standby and before any registers within the sensor have been changed from their default power-up values). general purpose inputs the MT9D014 provides four general purpose inputs. after reset, the input pads associ- ated with these signals are powered on by de fault, requiring the pads to be tied to a defined logic level. the general purpose inputs are disabled by setting reset_register[8] (r0x301a?b). once disabled, the inputs can be left floating. the state of the general purpose inputs can be read through gpi_status[3:0] (r0x3026?7). in addition, each of the following functions ca n be associated with none, one, or more of the general purpose inputs so that the function can be directly controlled by a hardware input: ? trigger (see the following sections) ? standby functions (see the following sections) ?s addr selection (see ?serial register interface? on page 26). the gpi_status register is used to associ ate a function with a general purpose input. table 8: signal state during reset pad name pad type hardware standby software standby extclk input self biased. can be left disconnected/floating. reset_bar (xshutdown) input enabled. must be driven to a valid logic level. sclk input enabled. must be pulled up or driven to a valid logic level. s data i/o enabled as an input. must be pulled up or driven to a valid logic level. data_p output high-z. data_n output clk_p output clk_n output gpi[3:0] input powered up. must be connected to v dd or d gnd . test1 input must be driven to a logic 0. test2 input must be driven to a logic 1.
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 31 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor control of the signal interface preliminary streaming/standby control the MT9D014 can be switched between its soft standby and streaming states under pin or register control, as shown in table 9. se lection of a pin to use for the standby func- tion is described in ?general purpose inputs? on page 30. the state diagram for transi- tions between soft standby and streaming states is shown in figure 12 on page 28. table 9: streaming/standby standby streaming r0x301aCb[2] description disabled 0 soft standby disabled 1 streaming x0 soft standby 01 streaming 1x soft standby
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 32 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor clocking preliminary clocking the MT9D014 contains a pll for timing gene ration and control. the pll contains a prescaler to divide the input clock applied on extclk, a vco to multiply the prescaler output, and a set of dividers to generate the output clocks. profile 0 behavior aptina smia sensors are profile 2 sensors and have separate video timing and output clock domains. if the video timing and output clock domains are programmed with the same dividers, the part will operate in profile 0 mode as indicated by r0x30e?f[7]. for example, if equa- tion 1 is true, then the pll will have profile 0 behavior: profile0_behavior = (vt_sys_clk_div == op_sys_clk_div) (eq 1) & (vt_pix_clk_div == op_pix_clk_div) when the pll is programmed to be in profile 0 behavior then the output clock domain is connected internally to the video timing doma in thus ensuring that the sensor behave as an profile 0 sensor with respect to the pll. in profile 0 mode the number of bits between one sync code and the subsequent one are guaranteed to be equal. note that legacy sensors used the profile bit in the datapath_select register r0x306e[7] to set this behavior. the new behavior of profile 0 mode is equivalent with the old one once it is set by the host system.
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 33 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor clocking preliminary figure 13: MT9D014 smia profile 1/2 clocking structure notes: 1. the combinations vt_sys_clk_div = 1 and vt_pix_clk_div = (4,6,8,10) are also supported even though the capability register does not advertise this. 2. the pll_multiplier only accepts even values when ccp2_class is set to data/clock signalling. odd values will be rounded down to the first even number by setting lsb to 0. 3. the default value for vt_sys_clk_div is outside the range of legal values defined by the capability regis- ters. this results in correct behavior for the cases listed in note 1. the default setting is selected to ensure profile 0 behavior as default with the highest possible frame rate. the parameter limit register space contains registers that declare the minimum and maximum allowable values for: ? the frequency allowable on each clock ? the divisors that are used to control each clock the following factors determine what are vali d values, or combinations of valid values, for the divider/multiplier control registers: ? the minimum/maximum frequency limits for the associated clock must be met. ? the minimum/maximum value for the divider/multiplier must be met. ? the value of pll_multiplier should be a multiple of 2 for data/strobe signalling. ? the op_pix_clk must never run faster than the vt_pix_clk to ensure that the ccp2 output data stream is contiguous. ? given the maximum programmed line length, the minimum blanking time, the maximum image width, the available pll di visor/multiplier values, and the require- ment that the output line ti me (including the necessary bl anking) must be output in a time equal to or less than the time defined by line_length_pck, the valid combinations of the clock divisors. pll input clock frequency range, after the pre-pll divider stage, is 2.0?11.5 mhz. the usage of the output clocks is: ? vt_pix_clk is used by the sensor core to control the timing of the pixel array. the sensor core produces one 10-bit pixel each vt_pix_clk period. the line length pre pll divider vt _sys_clk divider pll multiplier vt _ pix _clk divider op_sys _clk divider op _pix _clk divider op_pix_clk extclk external input clock pll input clock pll output clock video timing system clock op _ pix _clk _ div 10( 8, 10) pll_op_clk_freq_mhz pll_ip_clk_freq_mhz vt_sys_clk_freq_mhz vt_sys_clk_div 1 (2,4,6) vt_pix_clk op_sys_clk_div 1(1,2,4,6.......32) vt_sys_clk_freq_mhz op_sys_clk pll_multiplier 80(16,18 .....256) pre_pll_clk_div 2(1, 2, 3.....64) ext_clk_freq_mhz vt_pix_clk_div 10 (4, 5, 6......10) 1
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 34 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor clocking preliminary (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of the vt_pix_clk period. ? op_pix_clk is used to load parallel pixel data from the output fifo (see figure 23 on page 50) to the ccp2 serializer. the output fifo generates one pixel each op_pix_clk period. the pixel is either 8-bit or 10-bit depending upon the output data format, controlled by r0x0112 -3 (ccp_data_format). ? op_sys_clk is used to generate the serial data stream on the ccp2 output. the rela- tionship between this clock frequency an d the op_pix_clk frequency is dependent upon the output data format. in profile 1/2, the output clock frequencies can be calculated as: (eq 2) (eq 3) (eq 4) figure 14: MT9D014 smia profile 0 clocking structure notes: 1. the legal range yielding profile 0 behavior is limited to the pll values where the vt domain equals the op domain. the vt_sys_clk_div values in the parentheses are therefore the legal values for both vt_sys_clk_div and op_sys_clk_div, and the vt_pix_clk_div values in the parentheses are legal values for both vt_pix_clk_div and op_pix_clk_div. 2. the default value for vt_sys_clk_div is outside the range of legal values defined by the capability regis- ters. this will result in correct behavior for the cases listed in note 1. the default setting is selected to ensure profile 0 behavior as default with the highest possible frame rate. when the video timing domain and the outp ut timing domain have the same divider values, the pll is equivalent to the smia profile 0 clocking structure. this is achieved by driving the op_sys_clk domain from the vt_sys_clk output and by driving the op_pix_clk domain from the vt_pix_clk output. vt_pix_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*vt_sys _clk_div*vt_pix_clk_div ------------------ --------------------- ---------------------- --------------------- ------------------ ------------- op_pix_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*op_sys _clk_div*op_pix_clk_div -------------------- --------------------- --------------------- --------------------- ------------------ --------------- - op_sys_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*op_sys_clk_div -------------------- --------------------- --------------------- ----------------- pre pll divider vt_sys_ clk divider pll multiplier vt_pix_clk divider extclk external input clock pll input clock pll output clock video timing system clock vt_sys_clk_div 1 (2,4,6) pll_op_clk_freq_mhz pll_ip_clk_freq_mhz vt_sys_clk_freq_mhz ext_clk_freq_mhz pll_multiplier 80 (16,18....256) pre_pll_clk_div 2 (1,2,3,4....64) vt_pix_clk vt_pix_clk_div 10 (8,10) op_sys_clk
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 35 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor clocking preliminary programming the pll divisors the pll divisors should be programmed while the MT9D014 is in the soft standby state. after programming the divisors, it is necessary to wait for the vco lock time before enabling the pll. the pll is enabled by entering the streaming state. an external timer needs to delay the entering of streaming mode by 1ms so that the pll can lock. the effect of programming the pll divisors while the MT9D014 is in the streaming state is undefined. influence of ccp_data_format r0x0112-3 (ccp_data_form at) controls whether the pixel data interface will generate 10 bits per pixel or 8 bits per pixel. the raw output of the sensor core is 10 bits per pixel; the two 8-bit modes represent a compressed data mode and a mode in which the two least significant bits of the 10-bit data are discarded. when the pixel data interface is generating 8 bits per pixel, op_pix_clk_div must be programmed with the value 8. when the pixel data interface is generating 10 bits per- pixel, op_pix_clk_div must be programmed with the value 10.
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 36 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor clocking preliminary influence of ccp2_signalling_mode r0x0111 (ccp2_signalling_mode) controls whet her the serial pixel data interface uses data/strobe signalling or data/clock signalling. when data/clock signalling is selected, the pll_multiplier supports both odd and even values. when data/strobe signalling is selected, th e pll_multiplier only supports even values; the least significant bit of the programmed value is ignored and treated as ?0.? this behavior is a result of the implementati on of the ccp serializer and the pll. when the serializer is using data/strobe signalling, it uses both edges of the op_sys_clk, and therefore that clock runs at one half of the bi t rate. all of the programmed divisors are set up to make this behavior invisible. for example, when the divisors are programmed to generate a pll output of 640 mhz, the actual pll output is 320 mhz, but both edges are used. when the serializer is using data/clock signalling, it uses a single edge on the op_sys_clk, and therefore that clock runs at the bit rate. to disguise this behavior from the programmer, the actual pll multiplier is right-shifted by one bit relative to the programmed valu e when ccp2_signallin g_mode selects data/ strobe signalling.
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 37 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary features shading correction (sc) lenses tend to produce images whose bright ness is significantly attenuated near the edges. there are also other factors causing fixed pattern signal gradients in images captured by image sensors. the cumulative result of all these factors is known as image shading. the MT9D014 has an embedded sh ading correction module that can be programmed to counter the shading effects on each individual red, greenb, greenr, and blue color signal. the correction function color-dependent solutions are calibrated using the sensor, lens system, and an image of an evenly illuminated, featureless grey cali bration field. from the resulting image the color correction functions can be derived. the correction functions can then be appl ied to each pixel value to equalize the response across the image as follows: (eq 5) where p are the pixel values and f is the color-dependent correction function for each color channel. each function includes a set of color-dependent coefficients defined by registers r0x3600?3726. the function's origin is the ce nter point of the function used in the calculation of the coefficients. using an origin near the central point of symmetry of the sensor response provides the best results. the correct sequence to write to the sc registers is as follows: 1. set r0x3780?1 = 0x0000. 2. load sc coefficients. 3. set r0x3780?1 = 0x8000. to read the sc coefficients, sc should be disabled (set r0x3780?1 = 0x0000) before reading the register values. image acquisition modes the MT9D014 supports ers mode. when the MT9D014 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. timing and control logic within the sensor sequences through th e rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is fixed, leading to a uniform inte gration time across the frame. when the integration time is changed (by using the two- wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the MT9D014 switches cleanly from the old integration time to the new while only generating frames with uniform inte- gration. pcorrected row, col () = psensor(row,col) * f(row,col)
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 38 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary window control the sequencing of the pixel array is cont rolled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. the ou tput image size is controlled by the x_output_size and y_output_size registers. pixel border the default settings of the sensor provide a 1600h x 1200v image. a border of up to 4 pixels on each edge can be enabled by re programming the x_addr_start, y_addr_start, x_addr_end, y_addr_end, and x_output_size and y_output_size registers accordingly. readout modes horizontal mirror when the horizontal_mirror bit is set in the image_orientation register, the order of pixel readout within a row is reversed, so that re adout starts from x_addr_end and ends at x_addr_start. figure 15 shows a sequence of 6 pixels being read out with horizontal_mirror = 0 and horizontal_mirror = 1. changing horizontal_mirror causes the bayer order of the output image to change; th e new bayer order is reflected in the value of the pixel_order register. figure 15: effect of horizontal_mirror on readout order vertical flip when the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. figure 16 shows a sequence of 6 rows being read out with vertical_flip = 0 and vertical_flip = 1. changing vertical_flip causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 16: effect of vertical_flip on readout order g0 [9:0] r0 [9:0] g1 [9:0] r1 [9:0] g2 [9:0] r2 [9:0] r2 [9:0] g2 [9:0] r1 [9:0] g1 [9:0] r0 [9:0] g0 [9:0] line_valid horizontal_mirror = 0 d out (9:0) horizontal_mirror = 1 d out (9:0) row0 [9:0] row1 [9:0] row2 [9:0] row3 [9:0] row4 [9:0] row5 [9:0] row5 [9:0] row4 [9:0] row3 [9:0] row2 [9:0] row1 [9:0] row0 [9:0] frame_valid vertical_flip = 0 d out( 9:0) vertical_flip = 1 d out (9:0)
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 39 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary subsampling the MT9D014 supports subsampling. subs ampling reduces the amount of data processed by the analog signal chain in the MT9D014 thereby allowing the frame rate to be increased. subsampling is enabled by se tting x_odd_inc and/or y_odd_inc. values of 1 and 3 can be supported. setting both of th ese variables to 3 reduces the amount of row and column data processed. figure 17 shows a sequence of 8 columns being read out with x_odd_inc = 3 and y_odd_inc = 1. figure 17: effect of x_odd_inc = 3 on readout sequence figure 18: pixel readout (no subsampling) g0 [9:0] r0 [9:0] g1 [9:0] r1 [9:0] g2 [9:0] r2 [9:0] g3 [9:0] r3 [9:0] g0 [9:0] r0 [9:0] g2 [9:0] r2 [9:0] line_valid x_odd_inc = 1 d out [9:0] line_valid x_odd_inc = 3 d out [9:0] x incrementing y incr ementing
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 40 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary figure 19: pixel readout (x_odd_inc = 3, y_odd_inc = 3) programming restrictions when subsampling when subsampling is enabled as a viewfinder mode and the sensor is switched back and forth between full resolution and subsampling, aptina recommends that line_length_pck be kept consta nt between the two modes. this allows the same integra- tion times to be used in each mode. when subsampling is enabled, it may be necessary to adjust the x_addr_end, x_addr_start and y_addr_end settings: the va lues for these registers are required to correspond with rows/columns that form part of the subsampling sequence. the adjust- ment should be made in accordance with the following rules: ? x_addr_start must be a multiple of 2 for example 0, 4, 6, 8, and x_addr_start = 2 is not supported example: to achieve 1600 x 1200 full resolution with out subsampling, the recommended register settings are: [full resolution starting address with (4, 4)] reg=0x0104, 1 //grouped_parameter_hold reg=0x0382, 1 //x_odd_inc reg=0x0386, 1 //y_odd_inc reg=0x0344, 4 //x_addr_start reg=0x0346, 4 //y_addr_start reg=0x0348, 1603 //x_addr_end reg=0x034a, 1203 //y_addr_end reg=0x034c, 1600 //x_output_size reg=0x034e, 1200 //y_output_size reg=0x0104, 0 //grouped_parameter_hold x incrementing y i ncrementing
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 41 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary to achieve a 800 x 600 resolution with 1/2 subsampling, the recommended register settings are: table 10 shows the row address sequencing for normal and subsampled readout. the same sequencing applies to column addresses for subsampled readout. there are two possible subsampling sequences for the rows (because the subsampling sequence only read half of the rows) depending upon the alignment of the start address. [1/2 subsampling starting address with (8, 8)] reg=0x0104, 1 //grouped_parameter_hold reg=0x0382, 3 //x_odd_inc reg=0x0386, 3 //y_odd_inc reg=0x0344, 8 //x_addr_start reg=0x0346, 8 //y_addr_start reg=0x0348, 1605 //x_addr_end reg=0x034a, 1205 //y_addr_end reg=0x034c, 800 // x_output_size reg=0x034e, 600 //y_output_size reg=0x0104, 0 //grouped_parameter_hold table 10: row address sequencing odd_inc = 1 odd_inc = 3 normal normal start = 0 start = 0 start = 2 00 11 22 33 44 55 66 77 88 99 10 10 11 11 12 12 13 13 14 14 15 15
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 42 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary frame rate control the formula for calculating the frame rate of the MT9D014 are shown below: (eq 6) (eq 7) (eq 8) integration time the integration (exposure) time of the MT9D014 is controlled by the fine_integration_ time and coarse_integrat ion_time registers. the limits for the fine inte gration time are defined by: (eq 9) the limits for the coarse integration time are defined by: (eq 10) if coarse_integration_time > (frame_lenth_l ines-coarse_integration_time_max_margin), then the frame rate will be reduced. the actual integratio n time is given by: (eq 11) with a vt_pix_clk of 64 mhz, the maximum integration time that can be achieved without reducing the frame rate is given by: (eq 12) setting an integration time that is greater than the frame time increases the frame time beyond frame_leng th_lines to make longer exposure times available. line_length_pck x_addr_end - x_addr_start x_odd_inc + subsampling factor -------------------- --------------------- --------------------- ------------------ ----------------- - min_line_blanking_pck + ?? ?? = f rame_length_lines y_addr_end - y_addr_start y_odd_inc + subsampling factor --------------------- --------------------- ---------------------- ----------------- ---------------- - min_frame_blanking_lines + ?? ?? = f rame rate [fps] vt_pixel_clock_mhz * 1 6 10 () line_length_pck* frame_length_lines () --------------------- --------------------- ------------------ ----------------- ----------------- - = f ine_integration_time_min < = fine_integration_time < = line_length_pck-fine_integration_time_max_margin () coarse_integration_time_min < = coarse_integration_ t integration_time [sec] coarse_integration_time * line_length_pck () fine_integration_time + () vt_pix_clk_freq_mhz*1*10 6 () ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------- = maximum integration time [sec] = (( frame_length_lines -1 () * line_length_pck) + (line_length_pck - fine_integration_time_max_margin) vt_pix_clk_freq_mhz * 1* 10 6 () -------------------- --------------------- ----------------- ------------------ ------------------ ----------------- ---------------- -------------------- --------------------- --------------------- --------------------- ---------------------- ------------------ = 0x04c3-1 () *0x0888 () +0x797 () 64 mhz*1*10 6 () --------------------------------------------------------------------------------------------- 41.59ms =
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 43 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary analog gain the MT9D014 provides two mechanisms for setting the analog gain. the first uses the smia gain model; the second uses the traditional aptina imaging gain model. the following sections describe both models, the mapping between the models, and the operation of the per-color and global gain control. using per-color or global gain control the read-only analogue_gain_capa bility register returns a value of ?1,? indicating that the MT9D014 provides per-color gain control. however, the MT9D014 also provides the option of global gain control. per-color an d global gain control can be used interchange- ably. a write to a global gain register is alia sed as a write of the same data to the four associated color-dependent gain registers. a read from a global gain register is aliased to a read of the associated greenb/greenr gain register. the read/write gain mode register required by smia has no defined function in the smia specification. in the MT9D014 this register has no side effects on the operation of the gain; per-color and global gain control can be used interchangeably regardless of the state of the gain_mode register. smia gain model the smia gain model uses the following registers to set the analog gain: ? analogue_gain_code_global ? analogue_gain_code_greenr ? analogue_gain_code_red ? analogue_gain_code_blue ? analogue_gain_code_greenb the smia gain model requires a uniform step size between all gain settings. the analog gain is given by: (eq 13) aptina imaging gain model the aptina imaging gain model uses the following registers to set the analog gain: ? global_gain ?greenr_gain ? red_gain ? blue_gain ?greenb_gain this gain model maps directly to the control settings applied to the gain stages of the analog signal chain. this prov ides a 7-bit gain stage and a number of 2x gain stages. as a result, the step size varies depending upon whether the 2x gain stages are enabled. the analog gain is given by: (eq 14) gain = analogue_gain_m0 x analogue_gain_code analogue_gain_c1 ------------------- --------------------- --------------------- --------------------- ------------------- - analogue_gain_code_ 8 --------------------- --------------------- ----------------- --------------- = gain _gain[7] 1 + () _gain[6:0] 16 ----------------- ----------------- ------------ - =
pdf: 0526161444/source:6112702771 aptina reserves the right to change products or specifications without notice. mt0d014_ds - rev. j 5/10 en 44 ?2007 aptina imaging corporation. all rights reserved. MT9D014: 1/4-inch 2mp cmos digital image sensor features preliminary as a result of the 2x gain stage, many of the possible gain settings can be achieved in two different ways. for example, red_gain = 0x90 provides the same gain as red_gain = 0x20. the first example uses the 2x gain stage and the second example does not. in all cases, the preferred setting is the setting that enables the 2x gain stage, because this will result in lower noise. gain code mapping the aptina imaging gain model maps directly to the underlying structure of the gain stages in the analog signal chain. when the smia gain model is used, gain codes are translated into equivalent settings in the aptina imaging gain model. when the smia gain model is in use and values have been written to the analogue_gain_code_ registers, the as sociated value in the aptina imaging gain model can be read from the associated

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